As one of the integrated semiconductor memories embedded in an LSI, a nonvolatile memory is known. The nonvolatile memory is an element in which memory information is retained even when the LSI is turned off, and accordingly, it is a very important device when the LSI is employed for various applications.
Among nonvolatile memories of semiconductor devices, there are the so-called floating-gate memory and a memory using an insulating film. These memory cells are usually arranged in a matrix, and constitute an array (memory cell array) configured by a plurality of bit lines and word lines for use. Therefore, when a specified voltage is applied onto the bit lines and the word lines in order to program or erase a selected memory cell, a similar voltage gets to be also applied onto unselected memory cells that share the bit lines and the word lines. As a result, there is a possibility that a phenomenon such that a threshold value of the unselected memory cells is changed by the applied voltage, so-called miss-programming and miss-erase (disturbance) may occur.
U.S. Pat. No. 6,750,504 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. H01-115165 (Patent Document 2), disclose techniques to reduce the miss-programming and miss-erase, in which a well is isolated per bit line, and different voltages are applied onto the wells of selected memory cells for programming or erasing and onto the wells of the unselected memory cells, respectively. Meanwhile, in Patent Documents 1 and 2, power feeding to the well is made via a contact formed at an active edge (well edge).
In addition, in U.S. Pat. No. 4,870,470 (Patent Document 3), an n type diffusion layer (drain) is formed in an n type well, and an n type diffusion layer (source) is formed via a p type well. It is disclosed that the p type well is connected with the n type diffusion layer (source) by a contact that penetrates through the n type diffusion layer (source).
In such memory cells described in Patent Documents 1 and 2 mentioned above, along with reduction of the memory cell size, as the active width (that is, each well width dividing the wells) becomes narrow, the resistance of the well increases, and it is thought that it is hard to supply power from the contact for the wells formed at the active edge. In other words, the effects to reduce the disturbances become different due to the voltage drop in a distance from the contact to the channel region of each memory cell, and accordingly, there is a possibility that the effects to reduce the disturbances may decline extremely, in particular, with respect to the memory cells provided away from the contact may decline extremely.
As countermeasures against the increase of well resistance along with size reduction, in order to supply a desired voltage to the respective wells isolated for each bit line, it is considered to form a plurality of contacts for merely supplying power to the wells with respect to one bit line, and to reduce the number of the memory cells to be connected to one bit line, and so forth. However, by these countermeasures, when arrays including the same number of cells are constituted, the layout areas thereof are increased inevitably.
In addition, against the difference of the voltage drop in a distance from the contact to the channel region of the respective memory cells, in such a memory cell as described in the Patent Document 3 mentioned above, it is considered that, by the contact that penetrates through to the wells to the n type diffusion layer (source), the voltage can be supplied not by power supply to the well from the active edge, but at the vicinity of the memory cells. However, because the n type well conductive with the n type diffusion layer (drain) covers the p type well, junction leakage at the time of reading increases.